1. Field of the Invention
Embodiments of the invention relate to the field of microprocessors, and more specifically, to data receivers.
2. Description of Related Art
In a source synchronous protocol for memory interface between a memory controller and a memory device, the data is sent from a source to a receiver together with a clock, or a data strobe. The receiver uses the data strobe to latch the data. In double pumped mode, the data is captured on the rising and falling edges of the data strobe. When the memory controller initiates a read, the memory device sends both the data and the data strobe edge aligned to the memory controller clock so that the memory controller may shift the incoming strobe 90 degrees to latch the data. However, noise that may occur during the sampling may cause the receiver to sample the wrong data, causing unreliable operations. Similar problems may exist for other strobing modes such as single and quad-pumped modes.
The data strobe may be delayed by a controllable time delay using a delay locked loop (DLL). The data strobe jitter, however, may propagate to the output. It is difficult to limit the delay within a minimum value and a maximum value of the data valid window. Lastly, the throughput delay does not scale well with high frequencies and the minimum delay may become a large factor. Traditional receiver techniques do not provide sufficient margin at higher frequencies to allow for a positive data valid window. When the alignment of the data and the strobe is skewed, the integrating receiver may evaluate incorrect data due to the non-ideal data valid window caused by the skew. Several factors may cause skewed alignment such as trace skew, system noise, dynamic random access memory (DRAM) duty cycle error, etc. These factors typically exist in high frequency operations, leading to unreliable data capture.